About SLM
SLM is a compute infrastructure company building supercapability systems. We're developing new classes of high-performance architectures that deliver advanced performance, precision, and physical resilience in extreme environments. Many of our operating conditions are where conventional computing fails: radiation fields that destroy standard electronics, temperature extremes, and power constraints that demand every design decision be justified.
Our first-generation systems target advanced performance in some of the most challenging physical environments, with hard deployment windows that won't reopen for years or close to more than a decade. The system engineering challenges are significant: advanced semiconductor processes pushed to physical limits, emerging memory technologies integrated in ways they haven't been before, multi-die systems coordinated through custom packaging, and software toolchains that extract maximum performance from novel hardware. We're a small team solving problems most engineers never get close to, move at a high cadence and with rigor, and ship systems that need to work the first time in environments where they can't be iterated upon after deployment.
About this role
You'll take processor designs from RTL to GDS, closing timing on blocks running at multi-gigahertz frequencies while meeting strict power budgets and specialized physical resilience layout requirements that don't exist in standard design flows.
This means owning floorplanning for high-performance compute blocks where placement decisions determine whether you meet timing. You'll drive place-and-route for designs with thousands of instances, implement clock tree synthesis for low-skew distribution across large areas, and design power grids that deliver clean supply voltage to processing elements with rapidly varying current draw. And you'll do it all with specialized advanced material constraints that affect every decision: guard rings around sensitive logic, enclosed layout geometries for critical paths, spacing rules that differ from standard process design rules.
You'll work closely with the RTL designers to understand timing-critical paths and negotiate timing constraints that are aggressive but achievable. You'll collaborate with the foundry on design rule interpretations when standard PDK documentation doesn't cover specialized advanced material or physically-resilient structures. You'll iterate with the verification team when physical implementation reveals issues not caught in RTL simulation. You'll spend time debugging timing violations, IR drop problems, routing congestion, and DRC errors that arise from the intersection of high-performance design and specialized physical resiliency requirements.
The tools are standard — e.g. Cadence or Synopsys physical design flows — but the constraints are not. You need to understand what drives timing at advanced nodes, how to mitigate IR drop without wasting metal resources, how to achieve high utilization without creating routing congestion. You need to develop custom methodologies for specialized physical resiliency layout, working with the device physics team to understand which structures are most vulnerable and what mitigation techniques actually work.
What we're looking for
- Strong background in physical design with experience closing timing on complex blocks at advanced process nodes.
- You've used industry-standard P&R tools, understand multi-corner multi-mode analysis, and have debugged real timing closure problems; not just run automated flows but understood why timing failed and how to fix it.
- You're comfortable with floorplanning, placement optimization, clock tree synthesis, and routing.
Experience at sub-10nm nodes is valuable — you understand finFET constraints, multi-patterning, and the other physical effects that dominate at advanced nodes. If you've worked on low-power designs or high-reliability systems, you've dealt with some of the conflicting constraints we're navigating. Familiarity with specialized physical resiliency layout techniques is a plus but not required; we can teach you the specific methodologies if you bring strong physical design skills.
We're looking for someone who takes ownership of timing closure, communicates proactively about risks and schedule, and works effectively across teams when physical implementation reveals issues with the RTL or floorplan.
What we offer
As an early team member, you'll shape capabilities and systems with first-order consequences for the future and direction of humanity's enterprise.
This is accompanied by a strong equity package, competitive base salary, and comprehensive benefits including enhanced healthcare coverage for you and your family, robust family planning support, life insurance, flexible time off and paid holidays, retirement plans with matching, daily meals at our headquarters, and relocation support.
Our primary operational base is set in the Bay Area, and our labs are headquartered in a part of the city set beside cypress groves and coastal trails. We work intensely but deliberately invest in removing avoidable frictions from your life so you can dedicate maximum bandwidth to your core work.
If we make you an offer, we will work hard to get you onto our team and can even sponsor visas and green cards once eligible.
We strongly encourage you to apply even if you feel you don't meet every qualification or attribute as described. We care more about evidence of strong ability and a high signal-to-noise ratio.
Role details
- Category: Silicon Design
- Role: Physical Design Engineer
- Work type: On-site
- Employment: Full-time
- Location: Bay Area, California
- Salary range: $170,000 - $240,000