About SLM
SLM is a compute infrastructure company building supercapability systems. We're developing new classes of high-performance architectures that deliver advanced performance, precision, and physical resilience in environments conditioned by hard physics. Many of our operating conditions are where conventional computing fails: ionization fields that destroy standard electronics, temperature extremes, and power constraints that demand every design decision be justified.
Our first-generation systems target advanced performance in some of the most challenging physical environments. We have a compressed timeline to execute deployment-ready systems, with hard deployment windows that won't reopen for years or close to more than a decade. We’re focused on optimizing these architecture platforms for sustained throughput in deterministic, real-time environments where a single error can invalidate months of data collection, gathered tactical provisions, and deployment certainties. This means fundamental architectural decisions about how processing elements coordinate, how memory hierarchies balance performance against ionization tolerance, and how heterogeneous dies communicate across advanced packaging.
We are operating on an accelerated timeline with high-stakes execution. Our principal architecture has been specified over three years of applied R&D, and now we're strengthening design, integration, production, and qualification to deliver deployment-ready systems. You'll work on problems most engineers never encounter: advanced process nodes with the constraints of physically-resilient advanced materials, new high-performance memory technologies that require proprietary foundry fabrication methods, integration challenges that need to be adapted for platform scalability and varying fixed SWaP specifications.
About this role
You'll design processor architectures that deliver large sustained compute in environments where extreme physical events happen continuously and every transistor you add increases the probability of a disastrous error. This means rethinking assumptions that work fine in commercial processors — how you structure processing elements, how you handle errors without sacrificing throughput, how you achieve deterministic real-time performance when extreme physical conditions can corrupt any storage element.
The architecture targets being being efficient enough to fit in constrained power budgets, dense enough to deliver the compute our customers need, and resilient enough to operate for years in ionizing-particle fields. You'll make fundamental microarchitecture decisions: datapath organization, memory hierarchy, interconnect topology, clock distribution, error detection and correction strategies. You're designing for sustained throughput under worst-case conditions, not peak performance in benchmarks.
You'll own the path from microarchitecture through physical implementation. This means working with the RTL team on how your architecture maps to synthesizable code, with the physical design team on floorplanning and timing methodology, with the verification team on what actually needs to be verified, with the DFT team on test access mechanisms. You need to understand what's achievable at advanced process nodes with unconventional advanced material constraints — enclosed layout rules, guard rings, specialized library cells that change your area and timing budgets.
The technical challenges are significant, but so is the autonomy. You'll have direct input on architecture decisions that define what the system can do. You'll work closely with the Platform Architect on system-level tradeoffs, but you direct processor microarchitecture. When conflicts arise between competing requirements — such as performance versus area, latency versus error resilience, determinism versus flexibility — you're making the calls with support from the broader team.
What we're looking for
- PhD or equivalent depth from shipping production silicon preferred.
- You've designed processor microarchitecture that went to tapeout — not just simulations, actual RTL that became physical gates.
- You understand the interplay between microarchitecture and physical implementation, between what looks good in RTL and what actually meets timing at advanced nodes.
- You've worked through the integration challenges that arise when your architecture meets everyone else's constraints.
Experience with spatial architectures, reconfigurable computing, or domain-specific processors is directly relevant. If you've worked on designs with strict real-time requirements or error resilience, you understand the tradeoffs you’ll have to navigate in this role. You should be comfortable with the fundamentals of varying physical conditions on digital circuits, or at minimum willing to develop that expertise rapidly working with our device physics team.
We're looking for someone who can move fast with incomplete information, make technical decisions that balance multiple constraints, and adjust course when reality differs from models. You'll need to be comfortable with significant technical responsibility and the intensity that comes with hard deadlines.
What we offer
As an early team member, you'll shape capabilities and systems with first-order consequences for the future and direction of humanity's enterprise.
This is accompanied by a strong equity package, competitive base salary, and comprehensive benefits including enhanced healthcare coverage for you and your family, robust family planning support, life insurance, flexible time off and paid holidays, retirement plans with matching, daily meals at our headquarters, and relocation support.
Our primary operational base is set in the Bay Area, and our labs are headquartered in a part of the city set beside cypress groves and coastal trails. Think natural light, fresh ocean air, and panoramic views. We work intensely but deliberately invest in removing avoidable frictions from your life so you can dedicate maximum bandwidth to your core work.
If we make you an offer, we will work hard to get you onto our team and can even sponsor visas and green cards once eligible.
We strongly encourage you to apply even if you feel you don't meet every qualification or attribute as described. We care more about evidence of strong ability and a high signal-to-noise ratio.
Role details
- Category: Silicon Design
- Role: SoC Architect
- Work type: On-site
- Employment: Full-time
- Location: Bay Area, California
- Salary range: $230,000 - $320,000