About SLM
SLM is a compute infrastructure company building supercapability systems. We're developing new classes of high-performance architectures that deliver advanced performance, precision, and physical resilience in environments conditioned by hard physics. Many of our operating conditions are where conventional computing fails: harsh environments orders of magnitude beyond what commercial electronics are designed for, temperature extremes, and reliability requirements that make every device physics decision critical.
Our systems need to survive and perform in particle radiation fields that cause ionization damage, displacement damage, and single-event effects in rapid succession. Incremental hardening of existing designs proves incompatible in our system’s operating settings, and we have to have robust understanding of device behavior at the physics level and build from that foundation. We're working at advanced process nodes where radiation response isn't fully characterized, integrating emerging memory technologies with complex radiation sensitivities, and validating everything through comprehensive test campaigns before deployment in environments where failure isn't recoverable.
Our principal capabilities have been specified and designed over three years of applied R&D, and we're now building production systems for scientific instrumentation with deployment deadlines measured in months instead of years. You'll work on device-level challenges that determine the entire system’s operational success: characterizing ionization response, developing predictive models, defining design rules that don't exist in standard foundry documentation.
About this role
You'll architect the memory hierarchy that determines whether our system can deliver the performance our customers need while surviving continuous exposure to harsh environmental conditions: integrating conventional SRAM with emerging mixed-precision technologies in ways that balance capacity, bandwidth, power, and physical resilience.
This means making fundamental decisions about cache hierarchy depth, capacity at each level, coherence protocols, error correction strategies, and scrubbing mechanisms. You'll evaluate new memory technologies, understanding their radiation response, retention characteristics, endurance limits, and integration requirements. You'll work with memory IP vendors and foundry partners to co-develop cells and controllers that don't exist in their standard offerings. You'll define memory controller microarchitecture that handles the complexity of multiple memory types with different access patterns, different error modes, and different harsh-environment sensitivities.
The technical challenges are substantial. Our advanced memory approaches offer density and retention but come with complex environmental-intensity response; some failure modes can be corrected with redundancy, others require architectural workarounds. You will need to design a memory system that exploits the strengths of each technology while mitigating their weaknesses, achieving the performance and capacity the system requires within power and area budgets.
You'll collaborate extensively across the team: with the SoC architects on memory interface specifications and bandwidth requirements, with the device physics team on understanding operating environment effects in different memory technologies, with the compiler team on how software can exploit the memory hierarchy, with technology partners on cell design and characterization. You'll make critical go/no-go decisions about which emerging memory technologies are ready for production use based on incomplete or evolving data from early characterization.
The timeline for this necessitates rigorous implementation. You'll need to make architecture decisions before all the data you'd like to have is available, establish partnerships with memory vendors before their technology is fully mature, and develop fallback plans for scenarios where the primary approach doesn't achieve the performance you need.
What we're looking for
- Advanced degree in Electrical Engineering or Computer Science with deep expertise in memory systems.
- You've architected memory hierarchies for high-performance systems, understand the physics and circuit design of different memory technologies, and have worked closely with memory IP vendors or foundries on integration challenges.
- You can evaluate technology tradeoffs across latency, bandwidth, capacity, power, and reliability; making informed decisions about architecture based on device-level characteristics.
Experience with SRAM, DRAM, and non-volatile memories is critical. If you've worked on systems with integrated materials, resource-constrained electronics, or high-reliability applications, you understand the additional constraints you’ll be operating under in your role. Familiarity with domain-specific acceleration, error correction codes, scrubbing mechanisms, and fault-tolerant memory architectures is directly applicable.
We're looking for someone who can navigate technical uncertainty, build strong partnerships with external vendors, and make architecture decisions that balance ideal performance against what's actually achievable. You should be comfortable with significant technical responsibility and the intensity of working toward hard deadlines.
What we offer
As an early team member, you'll shape capabilities and systems with first-order consequences for the future and direction of humanity's enterprise.
This is accompanied by a strong equity package, competitive base salary, and comprehensive benefits including enhanced healthcare coverage for you and your family, robust family planning support, life insurance, flexible time off and paid holidays, retirement plans with matching, daily meals at our headquarters, and relocation support.
Our primary operational base is set in the Bay Area, and our labs are headquartered in a part of the city set beside cypress groves and coastal trails. Think natural light, fresh ocean air, and panoramic views. We work intensely but deliberately invest in removing avoidable frictions from your life so you can dedicate maximum bandwidth to your core work.
If we make you an offer, we will work hard to get you onto our team and can even sponsor visas and green cards once eligible.
We strongly encourage you to apply even if you feel you don't meet every qualification or attribute as described. We care more about evidence of strong ability and a high signal-to-noise ratio.
Role details
- Category: Memory Systems
- Role: Memory Architect
- Work type: On-site
- Employment: Full-time
- Location: Bay Area, California
- Salary range: $230,000 - $320,000