About SLM
SLM is a compute infrastructure company building supercapability systems. We're developing new classes of high-performance architectures that deliver advanced performance, precision, and physical resilience in environments conditioned by extreme physics. Many of our operating conditions are where conventional computing fails: ionization fields that destroy standard electronics, temperature extremes, and power constraints that demand every design decision be justified.
Our first-generation systems target scientific instrumentation with hard deployment windows that won't reopen for years or close for more than a decade. The engineering challenges are significant: advanced semiconductor processes pushed to their limits, specialized memory technologies integrated in ways they haven't been before, multi-die systems coordinated through custom packaging, and software toolchains that extract maximum performance from novel hardware. We work as a focused team and solve problems most engineers never get close to, move at a high cadence and with rigor, and ship systems that need to work the first time in environments where you can't iterate after deployment.
About this role
You'll lead verification strategy for complex heterogeneous systems where functional correctness isn't negotiable. These systems deploy in environments where you can't debug hardware failures, where wrong answers invalidate months of operational data, where proving correctness before tapeout is essential.
This means building verification environments that achieve comprehensive coverage across multiple levels: unit-level verification for individual blocks, integration verification for how blocks communicate, system-level verification for end-to-end behavior. You'll develop constrained-random testbenches targeting corner cases that directed tests miss, implement formal property checking for critical protocols and state machines, and create emulation strategies for validating performance and timing before silicon arrives.
The verification challenges are substantial. You're verifying reconfigurable logic that can implement different functions depending on configuration, memory hierarchies with complex coherence protocols and error correction, interconnects with deadlock-freedom requirements and quality-of-service guarantees. You'll need to verify not just functional correctness but also field-specific and -agnostic error handling; that single-event upsets are detected and corrected, that error recovery mechanisms actually work, that the system continues operating despite continuous radiation exposure.
You'll work closely with RTL designers to understand design intent and identify areas of risk, with the architecture team to ensure verification priorities align with system requirements, with the software team to develop meaningful system-level test scenarios. You'll spend time writing verification IP and testbenches, analyzing coverage reports to identify verification gaps, debugging failures that could be test issues or actual design bugs, and driving coverage closure as tapeout approaches.
What we're looking for
- Extensive verification experience with expertise in UVM, SystemVerilog, and industry-standard verification methodologies.
- You've verified complex SoCs or system-level designs, achieved high coverage on real projects, and found bugs that mattered.
- You understand both constrained-random verification and formal methods, know when each approach is appropriate, and can develop comprehensive verification strategies that combine multiple techniques.
Experience verifying processors, memory subsystems, or interconnects is directly relevant; these are the types of blocks you’ll be working on. If you've worked with formal verification tools to prove protocol correctness or used emulation for system-level validation, those skills apply directly. Familiarity with error injection and fault simulation for testing error-resilient designs is valuable.
We're looking for someone who takes ownership of verification quality, communicates proactively about coverage gaps and schedule risks, and maintains high standards even under pressure to declare victory and move forward.
What we offer
As an early team member, you'll shape capabilities and systems with first-order consequences for the future and direction of humanity's enterprise.
This is accompanied by a strong equity package, competitive base salary, and comprehensive benefits including enhanced healthcare coverage for you and your family, robust family planning support, life insurance, flexible time off and paid holidays, retirement plans with matching, daily meals at our headquarters, and relocation support.
Our primary operational base is set in the Bay Area, and our labs are headquartered in a part of the city set beside cypress groves and coastal trails. We work intensely but deliberately invest in removing avoidable frictions from your life so you can dedicate maximum bandwidth to your core work.
If we make you an offer, we will work hard to get you onto our team and can even sponsor visas and green cards once eligible.
We strongly encourage you to apply even if you feel you don't meet every qualification or attribute as described. We care more about evidence of strong ability and a high signal-to-noise ratio.
Role details
- Category: Silicon Design
- Role: Design Verification Engineer
- Work type: On-site
- Employment: Full-time
- Location: Bay Area, California
- Salary range: $180,000 - $260,000