About SLM
SLM is a compute infrastructure company building supercapability systems. We're developing new classes of high-performance architectures that deliver advanced performance, precision, and physical resilience in environments conditioned by hard physics. Many of our operating conditions are where conventional computing fails: radiation fields that destroy standard electronics, temperature extremes, and power constraints that demand every design decision be justified.
Our first-generation systems target scientific instrumentation with hard deployment windows that won't reopen for years or close to more than a decade. This comes with substantial engineering challenges: advanced semiconductor processes pushed to accessible design limits, specialized memory technologies, multi-die systems coordinated through custom packaging, and software toolchains that extract maximum performance from novel hardware. We're a small, focused team solving problems most engineers never get close to, move at a high cadence, and ship systems that need to work the first time in environments where you can't iterate after deployment.
About this role
You'll design multi-die integration solutions that combine logic, memory, and specialized analog dies into coherent systems — using advanced packaging technologies to achieve capabilities impossible with monolithic integration while surviving extreme thermal and radiation environments.
This means architecting interposer-based 2.5D/3D packages where multiple dies communicate at high bandwidth through silicon or organic substrates, defining die stacking strategies that manage thermal hotspots in three-dimensional configurations, and designing heterogeneous integration approaches that combine different process technologies with different thermal expansion coefficients and different radiation sensitivities. You'll own the package from die placement through power delivery through thermal management through final assembly.
The technical challenges of this architecture span multiple physics domains. You need to design power delivery networks that provide clean, stable voltage to thousands of processing elements with rapidly varying current draw, distributed across multiple dies with different voltage requirements. You'll architect thermal solutions that extract heat from dense multi-die stacks operating across wide temperature ranges; sometimes cryogenic, sometimes elevated, always with limited cooling options. You'll design die-to-die interfaces that maintain signal integrity at high frequencies through interposer connections that experience radiation-induced leakage and degradation.
You'll work closely with the system integration team on electrical interfaces and bandwidth requirements, with SoC design on floorplanning and die partitioning decisions, with the device physics team on understanding radiation effects in package materials and interconnects, with OSAT partners on what's actually manufacturable and at what cost. You'll make critical decisions about technology choices — silicon interposer versus organic, microbump pitch, redistribution layer stack-up — balancing performance, cost, and manufacturability.
The constraints are tight. Package size affects system cost and thermal management options. Die-to-die bandwidth affects what the system architecture can be. Thermal resistance determines maximum power dissipation. Assembly yield affects economics. You need to help the team navigate all these constraints while maintaining the physical-resiliency tolerance and reliability that our applications and deployment settings demand.
What we're looking for
- Advanced degree in Electrical Engineering, Materials Science, or equivalent depth from industry experience.
- You've designed advanced packages for high-performance systems; not just supervised the work but actually done the engineering.
- You understand 2.5D integration technologies, interposer design, die stacking, microbumps, and redistribution layers.
- You can analyze thermal behavior using simulation tools, design power delivery networks that meet IR drop budgets, and work with assembly partners on process development.
Experience with chiplet architectures, heterogeneous integration, or multi-die systems is directly applicable. If you've worked on high-reliability or aerospace packaging where thermal cycling, vibration, or radiation are concerns, you understand the additional challenges we're addressing. Familiarity with package reliability physics — electromigration in microbumps, thermomechanical stress, moisture sensitivity — helps you design for long-term operation.
We're looking for someone who can balance competing constraints, communicate effectively across disciplines, and drive decisions when tradeoffs don't have clear answers. You should be comfortable with technical uncertainty as die designs evolve and comfortable working closely with external partners on technology development.
What we offer
As an early team member, you'll shape capabilities and systems with first-order consequences for the future and direction of humanity's enterprise.
This is accompanied by a strong equity package, competitive base salary, and comprehensive benefits including enhanced healthcare coverage for you and your family, robust family planning support, life insurance, flexible time off and paid holidays, retirement plans with matching, daily meals at our headquarters, and relocation support.
Our primary operational base is set in the Bay Area, and our labs are headquartered in a part of the city set beside cypress groves and coastal trails. Think natural light, fresh ocean air, and panoramic views. We work intensely but deliberately invest in removing avoidable frictions from your life so you can dedicate maximum bandwidth to your core work.
If we make you an offer, we will work hard to get you onto our team and can even sponsor visas and green cards once eligible.
We strongly encourage you to apply even if you feel you don't meet every qualification or attribute as described. We care more about evidence of strong ability and a high signal-to-noise ratio.
Role details
- Category: Heterogeneous Integration & Packaging
- Role: Advanced Packaging Engineer
- Work type: On-site
- Employment: Full-time
- Location: Bay Area, California
- Salary range: $190,000 - $270,000